The present invention relates to the manufacture of field programmable gate arrays, and other programmable logic devices. Specifically, a process is described which increases the manufacturing yield of semiconductor field programmable gate arrays.
The design of large-scale electronic systems has been facilitated through the use of field programmable gate arrays (FPGAs) and other programmable logic devices (PLDs). These arrays comprise generic logic devices that are configurable under control of configuration software to generate virtually any circuit design. FPGAs and PLDs offer a number of benefits, including relatively short design cycles, reduced costs as well as flexible reprogrammability.
As is the case with most semiconductor devices, the size of an FPGA or other PLD is determined by the manufacturing process. Manufacturing processes often have a very low yield, wherein only a small percentage of the manufactured FPGAs are good. The low yield increases the manufactured price for the FPGAs or other PLDs. The reason for such low yields is that devices must be defect-free to be fully functional. That is, if a single defect in one of the devices of the array occurs, the array itself is considered to be defective.
Various techniques have been developed to deal with isolated defects of an FPGA or other PLD. In one example, spare components are made available on the device which can be substituted for failed components. However, there is a penalty in that the device size must increase to accommodate the space required for spare components. This adversely affects yield.
Software techniques have been developed to design around individual components that have failed. When a failed component is discovered in the FPGA or other PLD during testing, the device may be marked as “in use” to make sure, when programming the FPGA or other PLD, the device is not programmed. Such a technique is shown in U.S. Pat. No. 6,530,071. In accordance with the subject matter of this reference, defect tolerance is addressed at the logic core/application level. In programming FPGAs or other PLDs, a design program is executed which includes executable code that both specifies a circuit design and generates a configuration bit file to implement the circuit design. The design program includes codes that selectively skip the configurable logic elements and resources that contain defects. However, as the number of defects increase, the ability to program the device decreases since more consideration must be given to avoid particular circuit elements that contain defects.